User guide

Name Direction Clock Domain Description
You must ground the data pins that are not active. For
single width configuration, the following bits are active:
• 32-bit FPGA fabric to PCS interface width: tx_
parallel_data[31:0]. Ground [127:32].
• 40-bit FPGA fabric to PCS interface width: tx_
parallel_data[39:0]. Ground [127:40].
• 63-bit FPGA fabric to PCS interface width: tx_
parallel_data[63:0] Ground [127:64].
For double width configuration, the following bits are
active:
• 40-bit FPGA fabric to PCS interface width:
data[103:64], [39:0]. Ground [127:104], [63:40].
• 64-bit FPGA fabric to PCS interface width:
data[127:64], [63:0].
Double-width mode is not supported for 32-bit, 50-bit,
and 67-bit FPGA fabric to PCS interface widths.
unused_tx_
parallel_data
Input
tx_clkout Port is enabled, when you enable Enable simplified
data interface. Connect all of these bits to 0. When
Enable simplified data interface is disabled, the
unused bits are a part of tx_parallel_data. Refer to
tx_parallel_data to identify the bits you need to
ground.
tx_control[<n>
<3>-1:0] or
tx_control[<n>
<18>-1:0]
Input Synchronous to
the clock driving
the write side of
the FIFO (tx_
coreclkin or
tx_clkout)
tx_control bits will have different functionality
depending on the transceiver configuration rule
selected. When Simplified data interface is enabled,
the number of bits in this bus will change, as the
unused bits will be shown as part of the unused_tx_
control port.
Refer to Enhanced PCS TX and RX Control Ports
section for more details.
unused_tx_
control[<n>
<15>-1:0]
Input Synchronous to
the clock driving
the write side of
the FIFO (tx_
coreclkin or
tx_clkout)
This port is enabled when you enable Enable
simplified data interface. Connect all of these bits to 0.
When Enable simplified data interface is disabled, the
unused bits are a part of the tx_control.
Refer to tx_control to identify the bits you need to
ground.
tx_err_ins Input tx_coreclkin
For the Interlaken protocol, you can use this bit to
insert the synchronous header and CRC32 errors if you
have turned on Enable simplified data interface.
When asserted, the synchronous header for that cycle
word is replaced with a corrupted one. A CRC32 error
is also inserted if Enable Interlaken TX CRC-32
generator error insertion is turned on. The corrupted
UG-01143
2015.05.11
Enhanced PCS Ports
2-55
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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