User guide

Enhanced PCS Ports
Figure 2-7: Enhanced PCS Interfaces
The labeled inputs and outputs to the PMA and PCS modules represent buses, not individual signals.
reconfig_reset
reconfig_clk
reconfig_avmm
TX Parallel Data, Control, Clocks
Enhanced PCS TX FIFO
Interlaken Frame Generator
Reconfiguration
Registers
TX Enhanced PCS
RX Enhanced PCS
Nios Hard
Calibration IP
TX PMA
Serializer
RX PMA
DeserializerCDR
tx_cal_busy
rx_cal_busy
Serial Data
Optional Ports
CDR Control
QPI
Serial Data
Clock
Generation
Block
tx_serial_clk0
(from TX PLL)
tx_analog_reset
RX Parallel Data, Control, Clocks
Enhanced PCS RX FIFO
Interlaken Frame Synchronizer
10GBASE-R BER Checker
Bitslip
Bitslip
rx_analog_reset
Clocks
PRBS
Optional Ports
Clocks
QPI
Arria 10 Transceiver Native PHY
In the following tables, the variables represent these parameters:
• <n>—The number of lanes
• <d>—The serialization factor
• <s>— The symbol size
• <p>—The number of PLLs
Table 2-41: Enhanced TX PCS: Parallel Data, Control, and Clocks
Name Direction Clock Domain Description
tx_parallel_
data[<n>128-
1:0]
Input Synchronous to
the clock driving
the write side of
the FIFO (tx_
coreclkin or
tx_clkout)
TX parallel data inputs from the FPGA fabric to the TX
PCS. If you select Enable simplified interface in the
Transceiver Native PHY IP Parameter Editor, tx_
parallel_data includes only the bits required for the
configuration you specify.
2-54
Enhanced PCS Ports
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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