User guide

Table 2-39: Calibration Status Ports
Name Direction Clock Domain Description
tx_cal_busy[<n>-1:0] Output Asynchronous When asserted, indicates that the
initial TX calibration is in progress.
For both initial and manual
recalibration, this signal will be
asserted during calibration and will
deassert after calibration is
completed. You must hold the
channel in reset until calibration
completes.
rx_cal_busy[<n>-1:0] Output Asynchronous When asserted, indicates that the
initial RX calibration is in progress.
For both initial and manual
recalibration, this signal will be
asserted during calibration and will
deassert after calibration is
completed.
Table 2-40: Reset Ports
Name Direction Clock Domain
(32)
Description
tx_analogreset[<n>-1:0] Input Asynchronous Resets the analog TX portion of the
transceiver PHY.
tx_digitalreset[<n>-1:0] Input Asynchronous Resets the digital TX portion of the
transceiver PHY.
rx_analogreset[<n>-1:0] Input Asynchronous Resets the analog RX portion of the
transceiver PHY.
rx_digitalreset[<n>-1:0] Input Asynchronous Resets the digital RX portion of the
transceiver PHY.
(32)
Although the reset ports are not synchronous to any clock domain, Altera recommends that you
synchronize the reset ports with the system clock.
UG-01143
2015.05.11
PMA Ports
2-53
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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