User guide

Name Direction Clock Domain Description
rx_pma_clkslip Output Clock A rising edge on this signal causes the RX deserializer
to slip the serial data by one clock cycle 2 unit intervals
(UI).
rx_pma_
qpipulldn[<n>-
1:0]
Input Asynchronous
This port is only used for Quick Path Interconnect
(QPI) applications.
rx_is_lockedto-
data[<n>-1:0]
Output rx_clkout
When asserted, indicates that the CDR PLL is locked
to the incoming data, rx_serial_data.
rx_is_
lockedtoref[<n>-
1:0]
Output rx_clkout
When asserted, indicates that the CDR PLL is locked
to the input reference clock.
rx_set_
locktodata[<n>-
1:0]
Input Asynchronous
This port provides manual control of the RX CDR
circuitry.
rx_set_
locktoref[<n>-
1:0]
Input Asynchronous
This port provides manual control of the RX CDR
circuitry.
rx_
seriallpbken[<n>
-1:0]
Input Asynchronous
This port is available if you turn on Enable rx_
seriallpbken port in the Transceiver Native PHY IP
core Parameter Editor. The assertion of this signal
enables the TX to RX serial loopback path within the
transceiver. This signal is enabled in Duplex or
Simplex mode. If enabled in Simplex mode, you must
drive the signal on both the TX and RX instances from
the same source. Otherwise the design fails compila‐
tion.
rx_prbs_done[<n>
-1:0]
Output rx_coreclkin
or rx_clkout
When asserted, indicates the verifier has aligned and
captured consecutive PRBS patterns and the first pass
through a polynomial is complete.
rx_prbs_err[<n>-
1:0]
Output rx_coreclkin
or rx_clkout
When asserted, indicates an error only after the rx_
prbs_done signal has been asserted. This signal gets
asserted for three parallel clock cycles for every error
that occurs. Errors can only occur once per word.
rx_prbs_err_
clr[<n>-1:0]
Input rx_coreclkin
or rx_clkout
When asserted, clears the PRBS pattern and deasserts
the rx_prbs_done signal.
2-52
PMA Ports
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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