User guide

Name Direction Clock Domain Description
tx_pma_
rxfound[<n>-1:0]
Output
Synchronous to
rx_coreclkin or
rx_clkout based
on the configura‐
tion.
This port is available if you turn on Enable tx_
rxfound_pma port (QPI) in the Transceiver Native
PHY IP core Parameter Editor. When asserted,
indicates that the receiver detect block in TX PMA
has detected a receiver at the other end of the
channel. Use this port for Quick Path Interconnect
(QPI) applications only.
rx_
seriallpbken[<n>
-1:0]
Input Asynchronous This port is available if you turn on Enable rx_
seriallpbken port in the Transceiver Native PHY IP
core Parameter Editor. The assertion of this signal
enables the TX to RX serial loopback path within the
transceiver. This signal can be enabled in Duplex or
Simplex mode. If enabled in Simplex mode, you
must drive the signal on both the TX and RX
instances from the same source. Otherwise the
design fails compilation.
Table 2-38: RX PMA Ports
Name Direction Clock Domain Description
rx_serial_
data[<n>-1:0]
Input N/A
Specifies serial data input to the RX PMA.
rx_cdr_refclk0 Input Clock
Specifies reference clock input to the RX clock data
recovery (CDR) circuitry.
Optional Ports
rx_cdr_refclk1–
rx_cdr_refclk4
Input Clock
Specifies reference clock inputs to the RX clock data
recovery (CDR) circuitry.
rx_pma_clkout Output Clock
This clock is the recovered parallel clock from the RX
CDR circuitry.
rx_pma_div_
clkout
Output Clock The deserializer generates this clock. This is used to
drive core logic, PCS-to-FPGA fabric interface, or
both. If you specify a rx_pma_div_clkout division
factor of 1 or 2, this clock output is derived from the
PMA parallel clock (low speed parallel clock). If you
specify a rx_pma_div_clkout division factor of 33, 40,
or 66, this clock is derived from the PMA serial clock.
This clock is commonly used when the interface to the
RX FIFO runs at a different rate than the PMA parallel
clock (low speed parallel clock) frequency, such as
66:40 applications.
rx_pma_iqtxrx_
clkout
Output Clock This port is available if you turn on Enable rx_ pma_
iqtxrx_clkout port in the Transceiver Native PHY IP
core Parameter Editor. This output clock can be used
to cascade the RX PMA output clock to the input of a
PLL.
UG-01143
2015.05.11
PMA Ports
2-51
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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