User guide

Name Direction Clock Domain Description
tx_serial_clk1
tx_serial_clk2
tx_serial_clk3
tx_serial_clk4
Inputs Clocks
These are the serial clocks from the TX PLL. The
frequency of these clocks depends on the data rate
and clock division factor. These additional ports are
enabled when you specify more than one TX PLL.
tx_pma_clkout Output Clock This clock is the low speed parallel clock from the
TX PMA. It is available when you turn on Enable
tx_pma_clkout port in the Transceiver Native PHY
IP core Parameter Editor.
(31)
tx_pma_div_
clkout
Output Clock If you specify a tx_pma_div_clkout division factor
of 1 or 2, this clock output is derived from the PMA
parallel clock (low speed parallel clock). If you
specify a tx_pma_div_clkout division factor of 33,
40, or 66, this clock is derived from the PMA serial
clock. This clock is commonly used when the
interface to the TX FIFO runs at a different rate than
the PMA parallel clock frequency, such as 66:40
applications.
tx_pma_iqtxrx_
clkout
Output Clock This port is available if you turn on Enable tx_ pma_
iqtxrx_clkout port in the Transceiver Native PHY IP
core Parameter Editor. This output clock can be
used to cascade the TX PMA output clock to the
input of a PLL.
tx_pma_
elecidle[<n>-
1:0]
Input Asynchronous When you assert this signal, the transmitter is forced
to electrical idle. This port has no effect when you
configure the transceiver for the PCI Express
protocol.
tx_pma_
qpipullup[<n>-
1:0]
Input Asynchronous This port is available if you turn on Enable tx_pma_
qpipullup port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. It is only used for Quick
Path Interconnect (QPI) applications.
tx_pma_
qpipulldn[<n>-
1:0]
Input Asynchronous This port is available if you turn on Enable tx_pma_
qpipulldn port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. It is only used for Quick
Path Interconnect (QPI) applications.
tx_pma_
txdetectrx[<n>-
1:0]
Input Asynchronous This port is available if you turn on Enable tx_pma_
txdetectrx port (QPI) in the Transceiver Native PHY
IP core Parameter Editor. When asserted, the
receiver detect block in TX PMA detects the
presence of a receiver at the other end of the channel.
After receiving the tx_pma_txdetectrx request, the
receiver detect block initiates the detection process.
Use this port for Quick Path Interconnect (QPI)
applications only.
(31)
This clock is not to be used for clocking the interface.
2-50
PMA Ports
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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