User guide

Parameter Range Description
Enable PCIe
pipe_rx_polarity
port
On / Off When you turn on this option, the pipe_rx_polarity input
control port is enabled. You can use this option to control
channel signal polarity for PCI Express configurations. When
the Standard PCS is configured for PCIe, the assertion of this
signal inverts the RX bit polarity. For other Transceiver
configuration rules the optional rx_polinv port inverts the
polarity of the RX bit stream.
Related Information
Standard PCS Ports on page 2-68
PCS Direct
Table 2-31: PCS Direct Datapath Parameters
Parameter Range Description
PCS Direct
interface width
8, 10, 16, 20, 32, 40,
64
Specifies the data interface width between the PLD and the
transceiver PMA.
Dynamic Reconfiguration Parameters
Dynamic reconfiguration allows you to change the behavior of the transceiver channels and PLLs without
powering down the device. Each transceiver channel and PLL includes an Avalon-MM slave interface for
reconfiguration. This interface provides direct access to the programmable address space of each channel
and PLL. Because each channel and PLL includes a dedicated Avalon-MM slave interface, you can
dynamically modify channels either concurrently or sequentially. If your system does not require
concurrent reconfiguration, you can parameterize the Transceiver Native PHY IP to share a single
reconfiguration interface.
You can use dynamic reconfiguration to change many functions and features of the transceiver channels
and PLLs. For example, you can change the reference clock input to the TX PLL. You can also change
between the Standard and Enhanced datapaths.
Table 2-32: Dynamic Reconfiguration
Parameter Value Description
Enable dynamic
reconfiguration
On/Off When you turn on this option, the dynamic reconfiguration
interface is enabled.
Share reconfigura‐
tion interface
On/Off When you turn on this option, the Transceiver Native PHY IP
presents a single Avalon-MM slave interface for dynamic reconfigu‐
ration for all channels. In this configuration, the upper [n:10]
address bits of the reconfiguration address bus specify the channel.
The channel numbers are binary encoded. Address bits [9:0]
provide the register offset address within the reconfiguration space
for a channel.
2-46
PCS Direct
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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