User guide

Table 2-25: Byte Serializer and Deserializer Parameters
Parameter Range Description
Enable TX byte
serializer
Disabled
Serialize x2
Serialize x4
Specifies the TX byte serializer mode for the Standard PCS. The
transceiver architecture allows the Standard PCS to operate at
double or quadruple the data width of the PMA serializer. The
byte serializer allows the PCS to run at a lower internal clock
frequency to accommodate a wider range of FPGA interface
widths. Serialize x4 is only applicable for PCIe protocol
implementation.
Enable RX byte
deserializer
Disabled
Deserialize x2
Deserialize x4
Specifies the mode for the RX byte deserializer in the Standard
PCS. The transceiver architecture allows the Standard PCS to
operate at double or quadruple the data width of the PMA
deserializer. The byte deserializer allows the PCS to run at a
lower internal clock frequency to accommodate a wider range
of FPGA interface widths. Serialize x4 is only applicable for
PCIe protocol implementation.
Table 2-26: 8B/10B Encoder and Decoder Parameters
Parameter Range Description
Enable TX 8B/
10B encoder
On / Off When you turn on this option, the Standard PCS enables the
TX 8B/10B encoder.
Enable TX 8B/
10B disparity
control
On / Off When you turn on this option, the Standard PCS includes
disparity control for the 8B/10B encoder. You can force the
disparity of the 8B/10B encoder using the tx_forcedisp
control signal.
Enable RX 8B/
10B decoder
On / Off When you turn on this option, the Standard PCS includes the
8B/10B decoder.
Table 2-27: Rate Match FIFO Parameters
Parameter Range Description
RX rate match FIFO
mode
Disabled
Basic 10-bit
PMA width
Basic 20-bit
PMA width
GbE
PIPE
PIPE 0 ppm
Specifies the operation of the RX rate match FIFO in the
Standard PCS.
UG-01143
2015.05.11
Standard PCS Parameters
2-41
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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