User guide

Table 2-24: TX and RX FIFO Parameters
Parameter Range Description
TX FIFO mode
low_latency
register_fifo
fast_register
Specifies the Standard PCS TX FIFO mode. The following
modes are available:
• low_latency: This mode adds 2-3 cycles of latency to the TX
datapath.
• register_fifo: In this mode the FIFO is replaced by registers
to reduce the latency through the PCS. Use this mode for
protocols that require deterministic latency, such as CPRI.
• fast_register: This mode allows a higher maximum
frequency (f
MAX
) between the FPGA fabric and the TX PCS
at the expense of higher latency.
RX FIFO mode
low_latency
register_fifo
The following modes are available:
• low_latency: This mode adds 2-3 cycles of latency to the RX
datapath.
• register_fifo: In this mode the FIFO is replaced by registers
to reduce the latency through the PCS. Use this mode for
protocols that require deterministic latency, such as CPRI.
Enable tx_std_
pcfifo_full port
On / Off Enables the tx_std_pcfifo_full port. This signal indicates
when the standard TX phase compensation FIFO has reached
full threshold. This signal is synchronous with tx_std_clkout.
Enable tx_std_
pcfifo_empty
port
On / Off Enables the tx_std_pcfifo_empty port. This signal indicates
when the standard TX phase compensation FIFO has reached
the empty threshold. This signal is synchronous with tx_std_
clkout.
Enable rx_std_
pcfifo_full port
On / Off Enables the rx_std_pcfifo_full port. This signal indicates
when the standard RX phase compensation FIFO has reached
the full threshold. This signal is synchronous with rx_std_
clkout.
Enable rx_std_
pcfifo_empty
port
On / Off Enables the rx_std_pcfifo_empty port. This signal indicates
when the standard RX phase compensation FIFO has reached
the empty threshold. This signal is synchronous with rx_std_
clkout.
2-40
Standard PCS Parameters
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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