User guide

• Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of Enhanced PCS on
page 2-279
• Interlaken on page 2-76
• 10GBASE-R and 10GBASE-R 1588
• 10GBASE-KR PHY IP Core on page 2-125
• Enhanced PCS Ports on page 2-54
Standard PCS Parameters
This section provides descriptions of the parameters that you can specify to customize the Standard PCS.
For specific information about configuring the Standard PCS for these protocols, refer to the sections of
this user guide that describe support for these protocols.
Table 2-23: Standard PCS Parameters
Note:
For detailed descriptions of the optional ports that you can enable or disable, refer to the Standard PCS
Ports on page 2-68 section.
Parameter Range Description
Standard PCS/
PMA interface
width
8, 10, 16, 20
Specifies the data interface width between the Standard PCS
and the transceiver PMA.
FPGA fabric/
Standard TX
PCS interface
width
8, 10, 16, 20, 32, 40 Shows the FPGA fabric to TX PCS interface width. This value is
determined by the current configuration of individual blocks
within the Standard TX PCS datapath.
FPGA fabric/
Standard RX
PCS interface
width
8, 10, 16, 20, 32, 40 Shows the FPGA fabric to RX PCS interface width. This value is
determined by the current configuration of individual blocks
within the Standard RX PCS datapath.
Enable Standard
PCS low latency
mode
On / Off Enables the low latency path for the Standard PCS. Some of the
functional blocks within the Standard PCS are bypassed to
provide the lowest latency. You cannot turn on this parameter
while using the Basic/Custom w/Rate Match (Standard PCS)
specified for Transceiver configuration rules.
UG-01143
2015.05.11
Standard PCS Parameters
2-39
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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