User guide

Chapter Document
Version
Changes Made
Arria 10
Transceiver PHY
Architecture
2014.08.15 Made the following changes
• Arria 10 PMA Architecture
• Added 2nd post-tap and pre-tap Pre-Emphasis signals .
• Updated DFE and CTLE modes of operation and Use
Models.
• Added new sections on How to Enable CTLE and How to
Enable DFE.
• Changed max data rate for GT channels to 28.3 Gbps in the
Receiver Buffer CTLE section.
• Updated Receiver Buffer figure by adding and modifying
Adaptive Parametric Tuning Engine to include CDR and
DFE.
• Updated VGA section that includes VGA Frequency
response for different gain settings.
• Arria 10 Enhanced PCS Architecture
• Changed references from MegaWizard to Parameters Editor.
• Arria 10 Standard PCS Architecture
• Removed the features not supported by 8B/10B Decoder.
• Changed the description of TX FIFO to include the depth of
the TX FIFO.
• Updated the description of Polarity Inversion feature to
include how to enable Polarity Inversion.
• Updated the description of Pseudo-Random Binary
Sequence (PRBS) Generator on the supported PCS-PMA
interface widths.
• Changed the value for Supported Word Aligner Pattern
Lengths for Bitslip Mode when the PCS-PMA Interface
Width is 8 in Table 5-8 Word Aligner Pattern Length for
Various Word Aligner Modes.
• Changed the description of RX FIFO to include the depth of
the RX FIFO.
• Changed the RX Word Aligner pattern length for PCS-PMA
interface width 8 in Bitslip Mode.
• Arria 10 PCI Express Gen3 PCS Architecture
• Corrected the low latency mode cycles of latency in the TX
FIFO (Shared with Standard and Enhanced PCS).
9-30
Document Revision History for Previous Releases
UG-01143
2015.05.11
Altera Corporation
Document Revision History for Current Release
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