User guide

Chapter Document
Version
Changes Made
• Updated Using PLLs and Clock Networks section
• Changed MegaWizard references to IP Catalog and
Parameter Editor.
• Updated the valid configurations for PLL IP and Native
PHY IP per 14.0A10 release change.
• Removed Table "xN Clock Network Data Rate Restrictions".
• Updated the chapter to indicate Arria 10 transceivers support to
fPLL to fPLL, fPLL to ATX PLL, and fPLL to CMU PLL
cascading.
Resetting
Transceiver
Channels
2014.08.15 Made the following changes:
• Updated the "Transmitter Reset Sequence After Power-Up" and
"Receiver Reset Sequence Following Power-Up" figures.
• Updated the "Resetting the Receiver During Device Operation"
procedure and associated figure.
• Updated the "Reset Sequence Timing Diagram for Transceiver
when CDR is in Manual Lock Mode" figure.
UG-01143
2015.05.11
Document Revision History for Previous Releases
9-29
Document Revision History for Current Release
Altera Corporation
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