User guide

Chapter Document
Version
Changes Made
• Changed the maximum data rate for GT channels to 28.3 Gbps.
• Changed figure "Arria 10 PLLs and Clock Networks" to indicate
channel 0,1,3, and 5 have only the CDR PLL.
• Updated figure "x1 Clock Lines" to indicate that the channel
PLL of channel 1 and channel 4 can be used as CMU PLL or as a
CDR.
• Updated ATX PLL, fPLL, and CMU PLL section with a clarifica‐
tion about input reference clock frequency stability at device
power-up.
• Updated Instantiating ATX PLL, fPLL, and CMU PLL topics
with new IP instantiation flow.
• Updated ATX PLL and fPLL architecture block diagrams to
show global clock or core clock as an input reference clock.
• Updated ATX PLL IP section with 14.0 A10 release changes
• Added fractional mode support.
• Added embedded debug parameters in table ATX PLL
Dynamic Reconfiguration.
• Updated fPLL IP section with 14.0A10 release changes
• Removed "fPLL -Clock Switch over Parameter and Settings"
table.
• Updated table "fPLL Parameter and Settings".
• Added embedded debug parameters in table "fPLL -
Dynamic Reconfiguration Parameters and Settings".
• Removed Number of auxiliary MCGB clock input ports
from fPLL IP parameters.
• Added global clock or core clock as an input reference clock
source.
• Added a new section for GLobal Clock or Core Clock as an Input
Reference Clock.
• Updated figure "Input Reference Clock Sources".
• Updated Dedicated Reference Clock Pins section "Dedicated
Reference Clock Pins".
• Added a connection to indicate that dedicated refclk pins
can drive the reference clock network.
• Removed a wrong connection from the diagram.
• Updated xN Clock Lines section with maximum channel span
limitations and added a exception for QPI protocols.
• Added a new image in the FPGA Fabric-Transceiver Interface
Clocking section.
• Added a new section for Channel Bonding describing PMA
bonding, PMA and PCS bonding in detail.
• Removed xN Clock Network Data Rate Restrictions table.
• Updated chapter to indicate Arria 10 Transceivers support fPLL
to fPLL, fPLL to ATX PLL, and fPLL to CMU PLL cascading.
9-28
Document Revision History for Previous Releases
UG-01143
2015.05.11
Altera Corporation
Document Revision History for Current Release
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