User guide

Chapter Document
Version
Changes Made
Other Protocols 2014.08.15 Made the following changes:
• Changed references from MegaWizard to IP Catalog or
Parameters Editor.
• Using the Basic and Basic with KR FEC Configurations of
Enhanced PCS
• Updated the "Transceiver Channel Datapath and Clocking
for Basic (Enhanced PCS) Configuration" figure and added
footnote 3.
• Updated the "General and Datapath Parameters", "TX PMA
Parameters", "RX PMA Parameters", and "Enhanced PCS
Parameters" tables.
• Added the "Equalization" table.
• Added the "How to Enable Low Latency in Basic Enhanced
PCS" section.
• Using the Basic/Custom, Basic/Custom with Rate Match
Configurations of Standard PCS
• Updated the values in the "Manual Mode when the PCS-
PMA Interface is 8 Bits", "Manual Mode when the PCS-PMA
Interface is 10 Bits", and "Manual Mode when the PCS-PMA
Interface is 16 Bits" figures.
• Added the "8B/10B Encoder and Decoder" and "8B/10B TX
Disparity Control" sections.
• Updated the "Connection Guidelines for a Basic/Custom
Design" figure.
• Updated the "General and Datapath Options Parameters",
"TX PMA Parameters", "RX PMA Parameters", and
"Standard PCS Parameters" tables.
• Design Considerations for Data Rates Above 17.4 Gbps Using
Arria 10 GT Channels
• Updated the maximum data rate for GT channels to 28.3
Gbps.
• Added information about PCS Direct mode.
• Updated "ATX PLL IP with GT Clock Lines Enabled" figure.
• Updated the How to Implement the Basic, Basic with Rate Match
Transceiver Configuration Rules in Arria 10 Transceivers
section.
Simulating the
Transceiver Native
PHY IP Core
2014.08.15 Made the following changes:
• Updated the "How to Use NativeLink to Specify a ModelSim-
Altera Simulation" section.
• Updated the "NativeLink Generated Scripts for Third-Party
RTL Simulation" table.
PLLs and Clock
Networks
2014.08.15 Made the following changes:
UG-01143
2015.05.11
Document Revision History for Previous Releases
9-27
Document Revision History for Current Release
Altera Corporation
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