User guide

Chapter Document
Version
Changes Made
• Updated the list of signals in the "Dynamic Reconfiguration
Interface Signals" table.
• Added new registers and updated descriptions of existing
registers in the "10GBASE-KR Register Definitions" table.
• Updated the 0x482 registers in the "PCS Registers" table.
• Updated and removed some addresses in the "PMA Registers"
table.
• Added the Speed Change Summary section.
• Removed the 10GBASE-KR, Backplane, FEC, GMII PCS
Registers section.
• Removed the 1588 Delay Requirement section.
• Removed the Channel Placement Guidelines section.
• Removed the introductory paragraph from the Design Example
section.
• Removed the 1588 FIFO block from the "Top Level Modules of
the 1G/10GbE PHY MegaCore Function" figure.
• Updated all values for ALMs, ALUTs, Registers, and M20K in
the "1G/10GbE PHY Performance and Resource Utilization"
table.
• Updated the blocks in the "Reconfiguration Block Details"
figure.
• Changed the blocks and clock connections in the "Clocks for
Standard and 10G PCS and TX PLLs" figure.
• Changed signal names and descriptions in the "Clock and Reset
Signals" table.
• Changed the parameter name for 10GbE Reference Clock
frequency and added the 1G Reference clock frequency
parameter in the "10GBASE-R Parameters" table.
• Removed the Set FEC_ability bit on power up and reset and
Set FEC_enable bit on power up and resetparameters from the
"FEC Options" table.
• Updated the list of available signals in the "1G/10GbE PHY
Top-Level Signals" figure.
• Added new registers and updated descriptions of existing
registers in the "10GBASE-KR Register Definitions" table.
• Added the 0x4A8 and 0x4A9 addresses and updated the name
for address 0x4A2 and 0x4A3 in the "10GBASE-KR, Backplane,
FEC GMII PCS Registers" table.
• Added the Speed Change Summary section.
UG-01143
2015.05.11
Document Revision History for Previous Releases
9-25
Document Revision History for Current Release
Altera Corporation
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