User guide

Table 2-11: Enhanced PCS TX FIFO Parameters
Parameter Range Description
TX FIFO Mode
Phase-Compensation
Register
Interlaken
Basic
Fast Register
Specifies one of the following modes:
• Phase Compensation: The TX FIFO compensates for
the clock phase difference between the read clock (rx_
clkout) and the write clocks (tx_coreclkin or tx_
clkout). TX FIFO write clock frequency and read clock
frequency depends on uneven gear ratios (like 64:40,
64:32 etc.), and tx_enh_data_valid control signal.
For uneven gear ratios, monitor the TX FIFO flags. For
the even gear ratios (like 64:64, 40:40 etc.), tie tx_enh_
data_valid to 1'b1.
• Register: The TX FIFO is bypassed. The tx_parallel_
data, tx_control and tx_enh_data_valid are
registered at the FIFO output. You must control tx_
enh_data_valid based on the gearbox ratio. If the gear
box ratio is uneven (like 66:40), control the tx_enh_
data_valid signal to inform gearbox that the TX data
is valid. Assert port 1'b1 at all times for even gearbox
ratio (like 64:64).
• Interlaken: The TX FIFO acts as an elastic buffer. In
this mode, there are additional signals to control the
data flow into the FIFO. Therefore, the FIFO write
clock frequency does not have to be the same as the
read clock frequency. You can control writes to the
FIFO with tx_enh_data_valid. By monitoring the
FIFO flags, you can avoid the FIFO full and empty
conditions. The Interlaken frame generator controls
reads.
• Basic: The TX FIFO acts as an elastic buffer to control
the input data flow, using tx_enh_data_valid. The
gearbox data valid flag controls the FIFO read enable.
• Fast Register: The TX FIFO allows a higher maximum
frequency (f
MAX
) between the FPGA fabric and the TX
PCS at the expense of higher latency.
TX FIFO partially
full threshold
10, 11, 12, 13, 14, 15 Specifies the partially full threshold for the Enhanced PCS
TX FIFO. Enter the value at which you want the TX FIFO
to flag a partially full status.
TX FIFO partially
empty threshold
1, 2, 3, 4, 5 Specifies the partially empty threshold for the Enhanced
PCS TX FIFO. Enter the value at which you want the TX
FIFO to flag a partially empty status.
Enable tx_enh_fifo_
full port
On / Off Enables the tx_enh_fifo_full port. This signal indicates
when the TX FIFO reaches the specified full threshold.
This signal is synchronous to tx_coreclkin.
UG-01143
2015.05.11
Enhanced PCS Parameters
2-31
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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