User guide

Chapter Document
Version
Changes Made
• Specified the target BER of 10
-12
in the 10GBASE-KR PHY IP
Core section.
• Removed the "Top Level Modules of the 1G/10GbE PHY
MegaCore Function" figure.
• Removed the 10GBASE-KR PHY with 1588 variant from the
"10GBASE-KR PHY Performance and Resource Utilization"
table. This is not supported.
• Replaced the "10GBASE-KR PHY IP Block Diagram" figure.
• Added the Auto Negotiation, IEEE 802.3 Clause 73 section.
• Substantially rewrote the Link Training (LT), IEEE 802.3 Clause
72 section.
• Removed the "TX Equalization for Link Partners" figure.
• Removed the "TX Equalization in Daisy Chain Mode" figure.
Daisy chain is not supported.
• Removed the Auto Negotiation section.
• Replaced the "Reconfiguration Block Details" figure.
• Removed the Initial Datapath, Enable internal PCS reconfi‐
guration logic, and Enable IEEE 1588 Precision time Protocol
parameters from the "General Options Parameters" table.
• Added the Reference clock frequency, Enable additional
control and status pins, Include FEC sublayer, Set FEC_
ability bit on power up and reset, and Set FEC_Enable bit on
power up and reset parameters to the "General Options
Parameters" table.
• Removed the 10GBASE-R Parameters section.
• Removed the 10M/100M/1Gb Ethernet Parameters section.
• Removed the Speed Detection Parameters section.
• Substantially changed the "Auto Negotiation and Link Training
Settings" table, adding the AN_PAUSE Pause Ability,
CAPABLE_FEC ENABLE_FEC (request), AN_TECH
Technology Ability, AN_SELECTOR Selector Field, and
Width of the Training Wait Counter parameters.
• Updated all parameter names, values, and descriptions in the
"Optional Parameters" table.
• Updated the signals in the "10GBASE-KR Top-Level Signals"
figure.
• Removed the rx_serial_clk_1g and tx_serial_clk_1g
signals, and removed all references to "1G" from all descriptions
in the "Clock and Reset Signals" table.
• Removed references to GMII and MII interfaces from the Data
Interfaces section.
• Removed GMII and MII signals from the "XGMII Signals"
table.
• Updated the list of signals in the "Control and Status Signals"
table.
• Removed the Daisy-Chain Interface Signals section.
• Removed the Embedded Processor Interface Signals section.
9-24
Document Revision History for Previous Releases
UG-01143
2015.05.11
Altera Corporation
Document Revision History for Current Release
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