User guide

Chapter Document
Version
Changes Made
Interlaken 2014.08.15 Made the following changes:
• Changed parameter name in the "Signals and Ports of Native
PHY IP for Interlaken" figure from tx_bonding_clock to tx_
bonding_clock[5:0].
• Updated tables in the "Native PHY IP Parameter Settings for
Interlaken" section:
• Added new tables: "10GBASE-R BER Checker Parameters",
"KR-FEC Parameters".
• Deleted table: "Configuration Profiles Parameters".
• Added new parameters and updated existing ones to tables:
"General and Datapath Parameters", "TX PMA Parameters",
"RX PMA Parameters", "Enhanced PCS Parameters",
"Dynamic Reconfiguration Parameters".
• Updated existing parameters to tables: "Interlaken Frame
Generator Parameters", "Interlaken CRC-32 Generator and
Checker Parameters".
Ethernet
2014.08.15 Made the following changes:
• Initial release of the XAUI PHY IP Core section.
• Changed the bus width between the FPGA fabric and PCS, and
added notes 3 and 4 to the "Transceiver Channel Datapath and
Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2" figure.
• Provided the full hexadecimal values for rx_parallel_data,
rx_patterndetect, and rx_runningdisp in the "Decoding for
GbE" figure description.
• Changed the note in the Rate Match FIFO for GbE section to
clarify the case where 200 ppm total is valid.
• Added the pll_cal_busy circuitry, updated signals, and added
a note to the "Connection Guidelines for a GbE/GbE with IEEE
1588v2 PHY Design" figure.
• Removed the Device and speed grade parameter from the
"General and Datapath Options" table.
• Changed the values for the PPM detector threshold parameter
and removed the Decision feedback equaliztion parameter in
the "RX PMA Parameters" table.
• Changed the 10GBASE-R PHY grouping in the "10GBASE-R
PHY as Part of the IEEE802.3-2008 Open System Interconnec‐
tion (OSI)" figure.
• Added that 10GBASE-R is compatible with the Altera 10-Gbps
Ethernet MAC Megacore Function in the 10GBASE-R,
10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC
Variants section.
• Added the "Transceiver Channel Datapath and Clocking for
10GBASE-R with IEEE 1588v2" figure.
• Changed steps 1 and 4 in the How to Implement 10GBASE-R,
10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC in
Arria 10 Transceivers section to match the GUI.
UG-01143
2015.05.11
Document Revision History for Previous Releases
9-23
Document Revision History for Current Release
Altera Corporation
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