User guide

Table 9-2: Document Revision History
Chapter Document
Version
Changes Made
Ethernet 2014.10.08 Changed the frequency for mgmt_clk in the "Avalon-MM Interface
Signals" table for 10GBASE-KR PHY IP Core with FEC Option and
for 1G/10 Gbps Ethernet PHY IP Core.
Other Protocols 2014.10.08 Removed an erroneous note regarding Quartus II software legality
check restrictions.
Reconfiguration
Interface and
Dynamic Reconfi‐
guration
2014.10.08 Made the following changes:
• Minor editorial changes. Corrected typographical errors in
Ports and Parameters and Native PHY IP Core Embedded Debug
sections.
• Corrected an error in "Example 6-1: Steps to Merge Transceiver
Channels" in Channel Merging Requirements section.
Arria 10
Transceiver PHY
Overview
2014.08.15 Made the following changes:
• Changed the maximum data rate for GT channels to 28.3 Gbps.
• Changed minimum data rate supported by GT transceiver
channels to 1 Gbps from 611 Mbps.
• Changed the figure "Arria 10 GX Devices with Six Transceiver
Channels and One PCIe Hard IP Block" to adda a clarification
about PCIe Hard IP block.
• Updated the legend for all figures in "Arria 10 GT Device
Transceiver Layout" section.
• Changed the device package names in Table1-3 and Table 1-4
in "Arria 10 GX and GT Device Package Details Section."
• Updated figure "Arria 10 SX Device with 48,36, and 24
Transceiver Channels and Two PCIe Hard IP Blocks.
• Updated figure "Arria 10 SX Devices with Six Transceiver
Channels and One PCIe Hard IP Block" to add a clarification
about PCIe Hard IP.
• Updated the device package names in Table 1-5 in "Arria 10 SX
Device Package Details" section.
• Removed all references of the note about PCS-Direct support
available in future release.
Transceiver
Design IP Blocks
2014.08.15 No changes made.
Transceiver
Design Flow
2014.08.15 Made the following changes:
• Added "Make Pin Assignments Using Pin Planner and
Assignment Editor" block to figure "Transceiver Design Flow"
• Updated Select and Instantiate PHY IP, Generate PHY IP, Select
and Instantiate PLL IP, and Generate PLL IP sections to indicate
the new IP instantiation flow per ACDS 14.0A10 release.
• Added a new section for Make Pin Assignments Using Pin
Planner and Assignment Editor
9-20
Document Revision History for Previous Releases
UG-01143
2015.05.11
Altera Corporation
Document Revision History for Current Release
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