User guide

Chapter Document
Version
Changes Made
Resetting Transceiver
Channels
2014.12.15 Made the following changes:
• Updated the "Transmitter Reset Sequence After Power-Up"
and "Transmitter Reset Sequence During Device Operation"
figures.
• Improved formatting in the "Transceiver PHY Reset
Controller IP Core Top-Level Signals" figure.
• Updated the description of the reset, tx_analogreset, and
rx_analogreset parameters in the "Top-Level Signals" table.
Arria 10 Transceiver
PHY Architecture
2014.12.15 Made the following changes:
Arria 10 PMA Architecture
• Added High Speed Differential I/O and Power Distribution
Network to the Transmitter Buffer circuitry.
• Added Power Distribution Network induced Inter-Symbol
Interference compensation.
• Replaced the figures related to Programmable Pre Emphasis
with a link to Pre Emphasis and Output Swing Settings
Estimator.
Arria 10 Standard PCS Architecture
• Changed the Standard PCS data rate from 12.5 Gbps to 12
Gbps.
Arria 10 PCI Express Gen3 PCS Architecture
• Updated TX FIFO in Transmitter Datapath.
• Changed the Standard PCS data rate from 12.5 Gbps to 12
Gbps.
Arria 10 Enhanced PCS Architecture
• Added PRBS7 Generator to support 64-bit width only.
• Updated the rule for tx_enh_data_valid control signal when
TX FIFO is used in phase compensation mode.
9-18
Document Revision History for Previous Releases
UG-01143
2015.05.11
Altera Corporation
Document Revision History for Current Release
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