User guide

Chapter Document
Version
Changes Made
Other Protocols 2014.12.15 Made the following changes:
Using the "Basic (Enhanced PCS)" and "Basic with KR FEC"
Configurations of Enhanced PCS
• Added four new sections: "TX Bit Slip", "TX Polarity
Inversion", "RX Bit Slip", and "RX Polarity Inversion".
Using the Basic/Custom, Basic/Custom with Rate Match
Configurations of Standard PCS
• Changed the initial value of tx_parallel_data in the
"Manual Mode when the PCS-PMA Interface Width is 10
Bits" and "Manual Mode when the PCS-PMA Interface
Width is 16 Bits" figures.
• Changed the minimum value for the "Data rate" parameter
to 1 Gbps in the "General and Datapath Options Parameters"
table.
Simulating the
Transceiver Native
PHY IP Core
2014.12.15 Made the following changes:
• In the introductory section, removed the third bullet in the
list of netlists you can simulate because gate-level timing
simulation is no longer supported.
• Removed mention of the ModelSim DE simulator in the
"How to Use NativeLink to Specify a ModelSim-Altera
Simulation" section.
PLLs and Clock
Networks
2014.12.15 Made the following changes:
• Added a note about PLL cascading support in ACDS 14.1
version of Quartus II software.
• Corrected the minimum data rate supported by ATX PLL in
Table: Transmit PLLs in Arria 10 Devices.
• Corrected the error in PLL output frequency range for ATX
PLL and CMU PLL IP cores.
• Corrected the PLL reference clock frequency range for ATX
PLL IP core.
• Added a note about jitter performance in Input Reference
Clock Sources section.
• Updated the Mix and Match Design Example figure to
indicate that MCGB is used in the example.
• Changed the minimum data rate supported by the PLLs to 1
Gbps.
UG-01143
2015.05.11
Document Revision History for Previous Releases
9-17
Document Revision History for Current Release
Altera Corporation
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