User guide

Chapter Document
Version
Changes Made
PCI Express 2014.12.15
• Added PIPE Gen3 32 bit PCS Clock Rates table in the Gen3
Rate Switchsection.
• Updated the Rate Switch Change figure.
• Updated the Bit Mappings When the Simplified Interface Is
Disabledtable.
• Updated the figures in How to Place Channels for PIPE
Configurations.
• Updated the Parameters for Arria 10 Native PHY IP in PIPE
Gen1, Gen2, Gen3 Modes - TX PMA table.
• Updated the clock domains in Signals and Ports of Native
PHY IP for PIPE figure.
• Updated the Ports for Arria 10 Transceiver Native PHY in
PIPE Mode table.
• Updated Logical PCS Master Channel for PIPE Configuration
table.
• Updated the PCIe Reverse Parallel Loopback in Gen1/Gen2
features with input signal name.
• Updated the Rate Switch Change figure.
• Updated the Gearbox Gen3 Transmission signals in the
Gen3 Data Transmission figure.
• Updated the PIPE Design Example section.
• Updated the Gen3 Power State Management P1 to P0
Transition signals.
• Updated the Supported Features for PIPE Configurations
table.
• Updated the Gen1/Gen2 Features section.
CPRI
2014.12.15
• Updated the parameter values for “RX word aligner mode”.
• Added a new option for Interlaken in the GUI "Enable
Interlaken TX random disparity bit".
• For PMA configuration rules changed the option “SATA” to
“SATA/SAS”.
• Changed the GUI option “CTLE adaptation mode” to “DFE
adaptation mode”.
9-16
Document Revision History for Previous Releases
UG-01143
2015.05.11
Altera Corporation
Document Revision History for Current Release
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