User guide

Chapter Document
Version
Changes Made
XAUI PHY IP Core 2014.12.15 Made the following changes:
• Added a PMA width requirement in the "Transceiver
Clocking and Channel Placement Guidelines in XAUI
Configuration" section.
• Changed the figure description for the "Transceiver
Clocking for XAUI Configuration" figure.
• Changed the note in the "Transceiver Clocking and Channel
Placement Guidelines in XAUI Configuration" section.
• Added a note to the "Transceiver Clocking for XAUI
Configuration With Phase Compensation FIFO Enabled"
figure.
• Added the "Transceiver Clocking for XAUI Configuration
With Phase Compensation FIFO Enabled" figure.
• Removed the Data rate parameter from the "General
Options" table.
• Removed the tx_digitalreset signal from the "Clock and
Reset Signals" table.
• Changed the available signals in the "PMA Channel
Controller Signals" table.
• Added the Enable phase compensation FIFO parameter to
the "Advanced Options" table.
• Added the pll_cal_busy_i signal to the "XAUI Top-Level
Signals—Soft PCS and PMA" figure.
• Added the xgmii_rx_inclk port to the "XAUI Top-Level
Signals—Soft PCS and PMA" figure.
• Changed the description in the "Clock and Reset Signals"
table.
• Removed the following signals from the "PMA Channel
Controller Signals" table:
• tx_bonding_clocks[5:0]
• pll_cal_busy_i
• pll_powerdown_o
• pll_locked_i
• Made the following changes to the "XAUI PHY IP Core
Registers" table.
• Removed cal_blk_powerdown
• Removed pma_tx_pll_is_locked
• Removed Word Addresses 0x082, 0x083, 0x086, 0x087,
0x088, 0x089
• Removed patterndetect[7:0]
• Changed the description for syncstatus [7:0]
• Added the xgmii_rx_inclk port to the "SDR RX XGMII
Interface " table.
• Added the pll_cal_busy_i port to the "PMA Channel
Controller Signals" table.
• Added the "XAUI PHY TimeQuest SDC Constraint" section.
UG-01143
2015.05.11
Document Revision History for Previous Releases
9-15
Document Revision History for Current Release
Altera Corporation
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