User guide

Parameter Range Description
FPGA fabric /
Enhanced PCS
interface width
32 , 40 , 50 , 64 , 66 ,
67
Specifies the interface width between the Enhanced PCS
and the FPGA fabric.
The 66-bit FPGA fabric to PCS interface width uses 64-bits
from the TX and RX parallel data. The block synchronizer
determines the block boundary of the 66-bit word, with
lower 2 bits from the control bus.
The 67-bit FPGA fabric to PCS interface width uses the 64-
bits from the TX and RX parallel data. The block synchron‐
izer determines the block boundary of the 67-bit word with
lower 3 bits from the control bus.
Enable Enhanced
PCS low latency
mode
On/Off Enables the low latency path for the Enhanced PCS. When
you turn on this option, the individual functional blocks
within the Enhanced PCS are bypassed to provide the
lowest latency path from the PMA through the Enhanced
PCS.
Enable RX/TX
FIFO double width
mode
On/Off Enables the double width mode for the RX and TX FIFOs.
You can use double width mode to run the FPGA fabric at
half the frequency of the PCS.
2-30
Enhanced PCS Parameters
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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