User guide

Chapter Document
Version
Changes Made
10GBASE-KR PHY
IP with FEC Option
2014.12.15 Made the following changes:
• Changed the "10GBASE-KR PHY IP Core Block Diagram"
figure to activate the Standard TX PCS, Standard RX PCS,
and GbE PCS blocks.
• Added a note to the "10GBASE-KR Functional Description"
section.
• Added new parameters to the "General Options" table.
• Changed the default values for VPOSTRULE, VPRERULE,
INITPOSTVAL, and INITPREVAL in the "Optional
Parameters" table.
• "10GBASE-KR PHY Register Definitions" table:
• Changed the default value for register address 0x4D0[7:4]
• Changed the default value for register address 0x4D0[17].
• Changed the descriptions for register address 0x4B2.
• Changed the descriptions for register addresses 0x4D5
and 0x4D6.
• Changed the descriptions for the following signals in the in
the "Clock and Reset Signals" table.
• tx_pma_clkout
• rx_pma_clkout
• tx_pma_div_clkout
• rx_pma_div_clkout
• Changed the descriptions for the following signals in the in
the "XGMII Signals" table.
• xgmii_tx_clk
• xgmii_rx_clk
• Removed the 1588 Soft FIFOs block from the "PHY-Only
Design Example with Two Backplane Ethernet and Two
Line-Side (1G/10G) Ethernet Channels" figure
1G/10 Gbps Ethernet
PHY IP Core
2014.12.15 Made the following changes:
• Changed the descriptions for register address 0x4D5 in the
"1G/10GbE Register Definitions" table.
• Removed the Daisy Chain and uP I/F lines from the Link
Training block in the "1G/10GbE PHY Block Diagram"
figure.
9-14
Document Revision History for Previous Releases
UG-01143
2015.05.11
Altera Corporation
Document Revision History for Current Release
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