User guide

Chapter Document Version Changes Made
Reconfiguration Interface
and Dynamic Reconfigura‐
tion
2015.05.11 Made the following changes:
• Completely revised, updated, and
reorganized the chapter.
• Added the following new sections:
• Multiple Reconfiguration Profiles
• Embedded Reconfiguration Streamer
• Arbitration
• Enabling and Disabling Loopback
Modes
• IP Guided Reconfiguration Flow
• On-Die Instrumentation
• Altera Debug Master Endpoint
• ODI Acceleration Logic
Analog Parameter Settings
2015.05.11 Made the following changes:
• Corrected typos in the Syntax descrip‐
tion of each parameter setting.
• Added the XCVR_A10_TX_SLEW_
RATE_CTRL parameter.
• Changed the available values for the
following parameters:
• XCVR_A10_TX_PRE_EMP_
SWITCHING_CTRL_PRE_TAP_1T
• XCVR_A10_TX_PRE_EMP_
SWITCHING_CTRL_1ST_POST_
TAP
• XCVR_A10_TX_PRE_EMP_
SWITCHING_CTRL_2ND_POST_
TAP
PLLs and Clock Networks
2015.05.11 Made the following changes:
• Updated ATX PLL, CMU PLL and FPLL
Configuration Options, Parameters and
Settings.
• Modified Transmit PLLs Data Rate
Range in Arria 10 Devices.
• Increased xN clock network channel
span.
• Added ATX PLL to fPLL cascading
details.
UG-01143
2015.05.11
Document Revision History for Current Release
9-11
Document Revision History for Current Release
Altera Corporation
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