User guide

Chapter Document Version Changes Made
• Enhanced PCS Ports
• Deleted ports tx_enh_fifo_cnt and
rx_enh_fifo_cnt from "Enhanced
PCS TX and RX FIFO" tables.
• Added "KR-FEC" table.
• Updated table name from "Bitslip" to
"Gearbox".
• Updated bit offset, functionality and
description for ports tx_control and
rx_control in tables "Bit Encodings
for Interlaken with Enable Simplified
Interfaced ON" and "Enable
Simplified Interfaced OFF".
• Updated bit offset, functionality and
description of ports tx_control and
rx_control in tables "Bit Encodings
for Basic Single Width Mode", "Bit
Encodings for Basic Double Width
Mode" and "Basic Mode".
• Updated TX control and RX control
bit encoding tables.
• Standard PCS
• Updated description for ports rx_
std_pcfifo_empty[<n>-1:0] and
rx_std_rmfifo_empty[<n>-1:0] in
"TX" and "RX FIFO", and "Rate
Match FIFO" tables.
• Updated direction of port rx_
datak[<n><w>/<s>-1:0] in "8B/10B
Encoder and Decoder" table.
• Deleted port rx_std_elecidle[<n>-
1:0] from "Bit Reversal and Polarity
Inversion" table.
• Merged "Signal Detection" in "Bit
Reversal and Polarity Inversion"
table.
• Added port tx_datak in "8B/10B
Encoder and Decoder" table.
UG-01143
2015.05.11
Document Revision History for Current Release
9-9
Document Revision History for Current Release
Altera Corporation
Send Feedback