User guide

Chapter Document Version Changes Made
• Enhanced PCS Parameters
• Removed the Enable rx_enh_fifo_
cnt port and Enable tx_enh_
fifo_cnt port parameters.
• Removed description of parameter
TX FIFO Mode for Register Mode
in "Enhanced PCS TX FIFO
Parameters" table.
• Added Error marking type
parameter in the "Gearbox
Parameters" table.
• Updated parameter name from
Enable Frame Burst to Enable
Frame Generator Burst Control
in the "Interlaken Frame Generator
Parameters" table.
• Updated description of parameter TX
FIFO Mode for Register Mode in
the "Enhanced PCS TX FIFO
Parameters" table.
• Updated pattern generators for
PRBS, Square Wave and PRP, PRBS
Checker and PRP Verifier sections.
• Standard PCS Parameters
• Deleted the description of fast_
register mode from "TX and RX
FIFO Parameters" table.
• Updated description for parameters
RX word aligner pattern length,
Enable rx_std_wa_a1a2size port
and Enable rx_std_bitslipboun-
darysel port in the "Word Aligner
and Bitslip Parameters" table.
• Added parameter Enable fast sync
status reporting for determin-
istic Latency SM in the "Word
Aligner and Bitslip Parameters" table.
• PCS Direct
• Added "PCS Direct" section to
describe the parameters available in
this option.
• Added the "PCS Direct" functional
block in the "General and Datapath
Parameters" section.
UG-01143
2015.05.11
Document Revision History for Current Release
9-7
Document Revision History for Current Release
Altera Corporation
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