User guide

Parameters Value Description
Enable rx_is_
lockedtoref port
On/Off Enables the optional rx_is_lockedtoref status output port.
This signal indicates that the RX CDR is currently locked to the
CDR reference clock. This is an asynchronous output signal.
Enable rx_set_
lockedtodata
port and rx_set_
lockedtoref
ports
On/Off Enables the optional rx_set_lockedtodata and rx_set_
lockedtoref control input ports. You can use these control
ports to manually control the lock mode of the RX CDR. These
are asynchronous input signals.
Enable rx_
seriallpbken
port
On/Off Enables the optional rx_seriallpbken control input port. The
assertion of this signal enables the TX to RX serial loopback
path within the transceiver. This is an asynchronous input
signal.
Enable PRBS
(Pseudo
Random Bit
Sequence)
verifier control
and status port
On/Off Enables the optional rx_prbs_err, rx_prbs_clr, and rx_
prbs_done control ports. These ports control and collect status
from the internal PRBS verifier.
Related Information
PLLs and Clock Networks on page 3-1
Channel Bonding on page 3-44
Continuous Time Linear Equalization (CTLE) on page 5-6
Decision Feedback Equalization (DFE) on page 5-9
Analog Parameter Settings on page 8-1
How to Enable CTLE and DFE on page 5-12
Enhanced PCS Parameters
This section defines parameters available in the Transceiver Native PHY GUI to customize the individual
blocks in the Enhanced PCS.
The following tables describe the available parameters. Based on the selection of the Transceiver
Configuration Rule , if the specified settings violate the protocol standard, the Transceiver Native PHY
IP core Parameter Editor prints error or warning messages.
Note:
For detailed descriptions about the optional ports that you can enable or disable, refer to the
Enhanced PCS Ports section.
Table 2-10: Enhanced PCS Parameters
Parameter Range Description
Enhanced PCS /
PMA interface
width
32 , 40 , 64 Specifies the interface width between the Enhanced PCS
and the PMA.
UG-01143
2015.05.11
Enhanced PCS Parameters
2-29
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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