User guide

Chapter Document Version Changes Made
PCI Express (PIPE) 2015.05.11 Made the following changes:
• Updated the "Transceiver Channel
Datapath for PIPE Gen1/Gen2 Configu‐
rations", "PIPE Gen1/Gen2/Gen3
Configurations", "PCIe Reverse Parallel
Loopback Mode Datapath", and "Signals
and Ports of Native PHY IP for PIPE"
figures.
• Updated "Rate Switch" Gen3 features.
• Updated the "Enable simplified
interface" and "Provide separate
interface for each channel" parameters
in the "Parameters for Arria 10 Native
PHY IP in PIPE Gen1, Gen2, Gen3
Modes" table.
• Updated the "PCS TX channel; bonding
master" parameters in the table
"Parameters for Arria 10 Native PHY IP
in PIPE Gen1, Gen2, Gen3 Modes - TX
PMA" table.
• Updated the "Selected CDR reference
clock frequency" parameter in the
"Parameters for Arria 10 Native PHY IP
in PIPE Gen1, Gen2, Gen3 Modes - RX
PMA" table.
• Updated "How to place channels for
PIPE configurations" section to include
placement guidelines for using Arria 10
PCIe Hard IP.
CPRI
2015.05.11 Made the following changes:
• Updated the "Connection Guidelines for
a CPRI PHY Design" figure.
• Added table for the "Behavior of word
aligner status signals for varying
interface widths", when in Manual
Mode.
9-4
Document Revision History for Current Release
UG-01143
2015.05.11
Altera Corporation
Document Revision History for Current Release
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