User guide

Chapter Document Version Changes Made
• Changed the bit to calibrate the fPLL
and changed "Avalon-MM interface" to
"internal configuration bus" in the
"Fractional PLL Recalibration" section.
• Changed "Avalon-MM interface" to
"internal configuration bus" in the
"CMU or CDR PLL Recalibration"
section.
• Changed the addresses in the "User
Recalibration" section.
• Changed the addresses in the "ATX PLL
Recalibration" section.
• Changed the addresses in the "Fractional
PLL Recalibration" section.
• Changed the addresses in the "CDR/
CMU PLL Recalibration" section.
• Changed the addresses and added
descriptions in the "PMA Recalibration"
section.
• Changed the addresses in the "Check
Calibration Status" section.
• Changed "Avalon-MM interface" to
"internal configuration bus" in the "PMA
Recalibration" section.
• Added the "Capability Registers" section.
10GBASE-R
2015.05.11 Made the following changes:
• Added a parameter to the "RX PMA
Parameters" table.
10GBASE-KR PHY IP
Core
2015.05.11 Made the following changes:
• Changed the following bits and descrip‐
tions in the "10GBASE-KR PHY Register
Definitions" section:
• Changed the bit and description for
address 0x4D0[21:20].
• Added address 0x4D0[22].
• Removed address 0x4D0[26:24].
• Added address 0x4D0[28:24].
• Removed addresses 0x4D0[27] and
0x4D0[28].
9-2
Document Revision History for Current Release
UG-01143
2015.05.11
Altera Corporation
Document Revision History for Current Release
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