User guide

Document Revision History for Current Release
9
2015.05.11
UG-01143
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This section provides the revision history for the chapters in this user guide.
Chapter Document Version Changes Made
Overview 2015.05.11 Changed lower limit of supported data rate
from 1.0 Gbps to 611 Mbps
Calibration 2015.05.11 Made the following changes:
• Changed register offsets globally.
• Changed the description in the "Reconfi‐
guration Interface and Arbitration with
PreSICE Calibration Engine" section.
• Changed the description in the "Calibra‐
tion Registers" section.
• Changed the descriptions and added a
bit in the "Avalon-MM Interface
Arbitration Registers" table.
• Changed the descriptions in the
"Transceiver Channel Calibration
Registers" table.
• Changed the descriptions in the
"Fractional PLL Calibration Registers"
table.
• Changed the descriptions in the "ATX
PLL Calibration Registers" table.
• Added the "Power-up Calibration
Sequence for Non-PCIe Hard IP (HIP)
Channels" and "Power-up Calibration
Sequence for PCIe HIP and non-PCIe
Channels" figures.
• Changed "Avalon-MM interface" to
"internal configuration bus" in the "User
Recalibration" section.
• Changed "Avalon-MM interface" to
"internal configuration bus" in the "ATX
PLL Recalibration" section.
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