User guide

Figure 7-3: Recalibration Sequence when the Transceiver Reference Clock or Data Rate Changes
fPLL Calibration
ATX PLL Calibration
RX Offset
Cancellation Calibration
TX Termination and Vod
Calibration
CDR / CMU Calibration
Calibration
Done
User Recalibration
User recalibration requires access to the internal configuration bus and calibration registers through the
Avalon-MM dynamic reconfiguration interface. Follow the steps below to perform a user recalibration.
1. Request access to the internal configuration bus by writing 0x2 to offset address 0x0[1:0].
2. Wait for reconfig_waitrequest to deassert (logic low).
3. Proceed to the next step if fPLL is not used in your application, otherwise:
a. Write 0x1 to bit[1] of offset address 0x100 of the fPLL.
b. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x3 to offset
address 0x0[1:0].
c. Wait for fpll_cal_busy and reconfig_waitrequest to deassert (logic low).
4. Proceed to the next step if ATX PLL is not used in your application, otherwise
a. Write 0x3 to bit[1:0] of offset address 0x100 of the ATX PLL.
b. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x1 to offset
address 0x0[0].
c. Wait for atxpll_cal_busy and reconfig_waitrequest to deassert (logic low).
5. Write 0x1 to bit[1], bit[2], bit[5] of offset address 0x100 of the PMA at once.
• Bit[1] is for CDR/CMU calibration enable.
• Bit[2] is for Offset Cancellation calibration enable.
• Bit[5] is for TX termination and Vod calibration enable.
6. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x3 to offset
address 0x0[1:0].
7. Wait for tx_cal_busy, rx_cal_busy and reconfig_waitrequest to deassert (logic low).
UG-01143
2015.05.11
User Recalibration
7-11
Calibration
Altera Corporation
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