User guide

Fractional PLL Recalibration
Follow these steps to recalibrate the Fraction PLL (fPLL):
1. Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[1:0].
2. Wait for reconfig_waitrequest to be deasserted (logic low).
3. To calibrate the fPLL, write 0x1 to bit[1] of address 0x100 of the fPLL.
4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x3 to offset
address 0x0[1:0]. Calibration is completed when cal_busy is deasserted (logic low).
5. Request access to the calibration registers by writing 0x2 to offset address 0x0[1:0].
6. Wait for reconfig_waitrequest to be deasserted (logic low).
7. Read address 0x101 to check the calibration status (pass or fail).
8. Release the internal configuration bus to PreSICE by writing 0x3 to offset address 0x0[1:0]. The fPLL
calibration is complete at this stage.
Note:
If you do not intend to check calibration status (pass or fail), you can skip steps 5 through 8.
CDR/CMU PLL Recalibration
Follow these steps to recalibrate the CDR/CMU PLL:
1. Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[1:0].
2. Wait for reconfig_waitrequest to be deasserted (logic low).
3. To recalibrate the CDR/CMU PLL, write 0x1 to bit[1] of address 0x100 of the CDR/CMU PLL.
4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x3 to offset
address 0x0[1:0]h. Calibration is completed when cal_busy is deasserted (logic low).
5. Request access to the calibration registers by writing 0x2 to offset address 0x0[1:0].
6. Wait for reconfig_waitrequest to be deasserted (logic low).
7. Read address 0x101 to check the calibration status (pass or fail).
8. Release the internal configuration bus to PreSICE by writing 0x3 to offset address 0x0[1:0]. The CMU
PLL calibration is complete at this stage.
Note:
If you do not intend to check calibration status (pass or fail), you can skip steps 5 through 8.
PMA Recalibration
PMA calibration includes:
• CDR/CMU PLL calibration
• RX offset cancellation calibration
• TX termination and Vod calibration
CDR calibration is required any time you change the RX line rate or clock frequency.
RX offset cancellation is dependent upon the CDR/CMU PLL. For example, if you recalibrate the
CDR/CMU PLL, Altera recommends that you recalibrate RX offset cancellation also.
TX termination is dependent upon Vod settings. For example, if you change Vod settings through the
transceiver tool kit or through the dynamic reconfiguration interface, Altera recommends that you
recalibrate the TX termination. This enables optimum transceiver performance.
UG-01143
2015.05.11
Fractional PLL Recalibration
7-9
Calibration
Altera Corporation
Send Feedback