User guide

The proper reset sequence is required after calibration. Altera recommends you use the Altera transceiver
reset controller IP which has tx_cal_busy and rx_cal_busy inputs. You need to connect tx_cal_busy
and rx_cal_busy from the native PHY outputs to the reset controller inputs in your design. Reset upon
calibration is automatically processed when you perform user recalibration.
Follow these steps to perform user recalibration:
1. Request internal configuration bus user access to the calibration registers by writing 0x2 to offset
address 0x0[1:0].
2. Wait for reconfig_waitrequest to be deasserted (logic low).
3. Set the required calibration enable bits by writing the proper value to offset address 0x100.
4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x3 to offset
address 0x0[1:0]. The reconfig_waitrequest signal is active high after PreSICE regains access.
Recalibration is in progress until the cal_busy signals are deasserted (logic low).
5. Request access to the calibration registers by writing 0x2 to offset address 0x0[1:0].
6. Wait for reconfig_waitrequest to be deasserted (logic low).
7. Check the calibration status (pass or fail) by reading offset address 0x101. You can also check if the
calibration enable bits are cleared by PreSICE by reading offset address 0x100.
8. Release the internal configuration bus to PreSICE by writing 0x3 to offset address 0x0[1:0]. After this
step, the recalibration process is complete.
Note: If you do not intend to check calibration status (pass or fail), you can skip steps 5 through 8.
Calibration Example
ATX PLL Recalibration
When you use the ATX PLL in your application, and it requires a line rate or clock frequency change, you
must recalibrate the ATX PLL after you have made the changes.
Follow these steps to recalibrate the ATX PLL:
1. Request user access to the internal configuration bus by writing 0x2 to offset address 0x0[1:0].
2. Wait for reconfig_waitrequest to be deasserted (logic low).
3. To calibrate the ATX PLL, write 0x1 to bit[0] of address 0x100 of the ATX PLL.
4. Release the internal configuration bus to PreSICE to perform recalibration by writing 0x3 to offset
address 0x0[1:0]. Calibration is completed when cal_busy is deasserted (logic low).
5. Request access to the calibration registers by writing 0x2 to offset address 0x0[1:0].
6. Wait for reconfig_waitrequest to be deasserted (logic low).
7. Read address 0x101 to check the calibration status (pass or fail).
8. Release the internal configuration bus to PreSICE by writing 0x3 to offset address 0x0[1:0]. The ATX
PLL calibration is complete at this stage.
Note:
If you do not intend to check calibration status (pass or fail), you can skip steps 5 through 8.
7-8
Calibration Example
UG-01143
2015.05.11
Altera Corporation
Calibration
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