User guide

Bit
PMA Calibration Enable Register Offset
Address 0x100
PMA Calibration Status Register Offset Address
0x101
7 Reserved Reserved
Fractional PLL Calibration Registers
Table 7-3: Fractional PLL Calibration Registers
Bit fPLL Calibration Enable Register Offset
Address 0x100
fPLL Calibration Status Register Offset Address
0x101
0 Reserved Reserved
1 fPLL calibration enable. Set 1 to enable
calibration.
fPLL calibration status
• 0x0 = Pass
• 0x1 = Fail
ATX PLL Calibration Registers
Table 7-4: ATX PLL Calibration Registers
Bit ATX PLL Calibration Enable Register
Offset Address 0x100
ATX PLL Calibration Status Register Offset
Address 0x101
0 ATX PLL calibration enable. Set 1 to
enable calibration.
ATX PLL calibration status
• 0x0 = Fail
• 0x1 = Pass
1 Reserved Reserved
Capability Registers
Capability registers allow you to read calibration status through the micro-controller. They are soft logic
and reside in the FPGA fabric.
To use capability registers to check calibration status, select the Enable capability registers option in the
Dynamic Reconfiguration tab. You must enable the capability registers when generating the Native PHY
or PLL IP cores.
Table 7-5: Capability Registers for Calibration Status
Bit Signal
0x281[1] PMA channel rx_cal_busy
0x281[0] PMA channel tx_cal_busy
0x280[1] ATX PLL pll_cal_busy
0x280[1] fPLL pll_cal_busy
Note: When you want to configure any of the register bits above, you must perform a read-modify-write
similar to the following examples.
7-4
Fractional PLL Calibration Registers
UG-01143
2015.05.11
Altera Corporation
Calibration
Send Feedback