User guide

Avalon-MM Interface Arbitration Registers
Table 7-1: Avalon-MM Interface Arbitration Registers
Bit Offset Address Description
[0] 0x0
(51)
This bit arbitrates the control of Avalon-MM interface.
• Set this bit to 0 to control the internal configuration
bus by user.
• Set this bit to 1 to pass the internal configuration bus
control to PreSICE.
[1] 0x0 This bit indicates whether or not calibration is done. This
is the inverted cal_busy signal. You can write to this bit;
however, if you accidentally write 1'b0 without requesting
calibration, PreSICE asserts cal_busy without return.
Channel reset is triggered if cal_busy is connected to the
reset controller.
• 0x1 = calibration done
• 0x0 = calibration not done
Transceiver Channel Calibration Registers
Table 7-2: Transceiver Channel PMA Calibration Registers
Bit
PMA Calibration Enable Register Offset
Address 0x100
PMA Calibration Status Register Offset Address
0x101
0 Reserved Reserved
1 CDR/CMU PLL calibration enable. Set 1 to
enable calibration.
CDR/CMU PLL calibration status
• 0x0 = Fail
• 0x1 = Pass
2 Receiver Offset Cancellation calibration
enable. Set 1 to enable calibration.
Receiver Offset Cancellation calibration
status
• 0x0 = Fail
• 0x1 = Pass
3 Reserved Reserved
4 Reserved Reserved
5 Transmitter termination and V
OD
calibration
enable. Set 1 to enable calibration.
Transmitter termination andVod calibra‐
tion status
• 0x0 = Fail
• 0x1 = Pass
6 Reserved Reserved
(51)
The transceiver channel, ATX PLL, and fPLL use the same offset address.
UG-01143
2015.05.11
Avalon-MM Interface Arbitration Registers
7-3
Calibration
Altera Corporation
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