User guide

To check if the calibration process is on, monitor the pll_cal_busy, tx_cal_busy, and rx_cal_busy
signals. The *_cal_busy signals remain asserted as long as the calibration process is running. Also, the
reconfig_waitrequest signal is asserted when the PreSICE controls the internal configuration bus for
calibration. The PMA tx_cal_busy and rx_cal_busy are from the same internal node which cannot be
separated from the hardware. If you want to differentiate tx_cal_busy and rx_cal_busy, design a small
circuit to do the following:
block tx_cal_busy when performing RX calibration
block rx_cal_busy when performing TX calibration
Related Information
Avalon Interface Specifications
Calibration Registers
The transceiver PMA and PLLs include the following types of registers for calibration:
Avalon-MM interface arbitration registers
Calibration enable registers
Calibration status registers
Capability registers
The Avalon-MM interface arbitration registers enable you to request internal configuration bus access. It
also provides a status bit to check the calibration status from the register read through the Avalon-MM
interface. Bit[1] of the arbitration register is the inverted cal_busy output signal.
The calibration enable registers for the transceiver PMA and PLLs enable one or more calibration
algorithms to be run when requested. These enable bits are mapped to offset address 0x100. All calibra‐
tion enable registers are self-cleared after the calibration process is completed.
The calibration status registers for the transceiver PMA and PLLs capture the status of a particular
calibration algorithm that was run at power-up or subsequently requested by you. These status bits are
mapped to offset address 0x101. All calibration status registers return a PASS or FAIL after calibration is
completed.
The tx_cal_busy, rx_cal_busy, ATX PLL pll_cal_busy, and fPLL pll_cal_busy signals are available
from the reading capability registers.
7-2
Calibration Registers
UG-01143
2015.05.11
Altera Corporation
Calibration
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