User guide

Calibration
7
2015.05.11
UG-01143
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Transceivers include both analog and digital blocks that require calibration to compensate for process,
voltage, and temperature (PVT) variations. Arria 10 transceiver uses hardened Precision Signal Integrity
Calibration Engine (PreSICE) to perform calibration routines.
Power-up Calibration and User Recalibration are the main types of calibration.
• Power-up calibration occurs automatically at device power-up. It runs during device configuration.
• If you perform dynamic reconfiguration, then you must perform User Recalibration. In this case, you
are responsible for enabling the required calibration sequence.
To successfully complete the calibration process, CLKUSR clocks must be stable and free running at start
of FPGA configuration. Also, all reference clocks driving the PLLs (ATX PLL, fPLL, CDR/CMU PLL)
must be stable and free running at start of FPGA configuration.
Reconfiguration Interface and Arbitration with PreSICE Calibration
Engine
Arria 10 transceiver channels and PLLs include a user-accessible Avalon-MM interface for dynamic
reconfiguration. It is used to access the channels and PLL's programmable registers and to interact with
the calibration engine. The Avalon-MM interface includes a communication mechanism to enable you to
request specific calibration sequences from the calibration controller.
In Arria 10 devices, calibration is performed using the Precision Signal Integrity Calibration Engine
(PreSICE). The PreSICE includes an Avalon-MM interface to access the transceiver channel program‐
mable registers and the PLL programmable registers. The user-accessible Avalon-MM and PreSICE
Avalon-MM interface share a single internal configuration bus. This bus is arbitrated to get access to the
channel and PLL programmable registers. Calibration registers can only be accessed by either the user-
accessible Avalon-MM interface or the PreSICE Avalon-MM interface because there is only one internal
configuration bus.
When PreSICE controls the internal configuration bus, the waitrequest signal is high. To request access
to the internal configuration bus, write 0x2 to address 0x0[1:0] of the channel or the PLL. When the access
is granted, the waitrequest signal goes low.
Note:
When you have access to the internal configuration bus, the continuous calibration routine is not
running. After all your user configuration requests are complete, you must pass the internal
configuration bus back to PreSICE. To release the internal configuration bus, write 0x3 to offset
address 0x0[1:0]. At this point, the continuous calibration routine starts running.
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