User guide

(initial profile and target profiles) during timing driven compilation. These timing arcs make the timing
more accurate.
When performing a dynamic reconfiguration, you must:
• Include constraints to create the extra clocks for all modified or target configurations at the PCS-FPGA
fabric interface. Clocks for the base configuration are created by the Quartus II software. These clocks
enable the Quartus II software to perform static timing analysis for all the transceiver configurations
and their corresponding FPGA fabric core logic blocks.
• Include the necessary false paths between the PCS – FPGA fabric interface and the core logic.
For example, you can perform dynamic reconfiguration to switch the datapath from Standard PCS to
Enhanced PCS using the multiple reconfiguration profiles feature. In the following example, the base
configuration uses the Standard PCS (data rate = 1.25 Gbps, PCA-PMA width = 10) and drives core logic
A in the FPGA fabric. The target or modified configuration is configured to use the Enhanced PCS (data
rate = 12.5 Gbps, PCS-PMA width = 64) and drives core logic B in the FPGA fabric.
Figure 6-16: Using Multiple Reconfiguration Profiles
Core Logic (A)
for Standard
PCS
Core Logic (B)
for Enhanced
PCS
Transceiver Channel
FPGA Fabric
tx_clkout
rx_clkout
Transmitter (TX)
Receiver (RX)
6-56
Timing Closure Recommendations
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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