User guide

Table 2-5: TX PLL Options
Parameter Value Description
TX local clock
division factor
1, 2, 4, 8 Specifies the value of the divider available in the transceiver
channels to divide the TX PLL output clock to generate the
correct frequencies for the parallel and serial clocks.
Number of TX
PLL clock inputs
per channel
1, 2, 3 , 4 Specifies the number of TX PLL clock inputs per channel. Use
this parameter when you plan to dynamically switch between
TX PLL clock sources. Up to four input sources are possible.
Initial TX PLL
clock input
selection
0- <number of TX
PLL clock inputs> -
1
Specifies the initially selected TX PLL clock input. This
parameter is necessary when you plan to switch between
multiple TX PLL clock inputs.
Table 2-6: TX PMA Optional Ports
Parameter Value Description
Enable tx_pma_
clkout port
On/Off Enables the optional tx_pma_clkout output clock. This is the
low speed parallel clock from the TX PMA. The source of this
clock is the serializer. It is driven by the PCS/PMA interface
block.
(27)
Enable tx_pma_div_
clkout port
On/Off Enables the optional tx_pma_div_clkout output clock. This
clock is generated by the serializer. You can use this to drive
core logic, to drive the FPGA - transceivers interface.
If you specify a tx_pma_div_clkout division factor of 1 or 2,
this clock output is derived from the PMA parallel clock. If you
specify a tx_pma_div_clkout division factor of 33, 40, or 66,
this clock is derived from the PMA high serial clock. This clock
is commonly used when the interface to the TX FIFO runs at a
different rate than the PMA parallel clock frequency, such as
66:40 applications.
Enable tx_pma_div_
clkout division factor
port
Disabled , 1 , 2 ,
33 , 40 , 66
Specifies the division factor for the tx_pma_div_clkout output
clock when this port is enabled.
Enable tx_pma_
iqtxrx_clkout port
On/Off Enables the optional tx_pma_iqtxrx_clkout output clock.
This clock can be used to cascade the TX PMA output clock to
the input of a PLL.
(27)
This clock should not be used to clock the FPGA - transceivers interface. This clock may be used as a
reference clock to an external clock cleaner.
UG-01143
2015.05.11
PMA Parameters
2-25
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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