User guide

Reconfigura‐
tion Address
(HEX)
Reconfigura‐
tion Bit
Attribute Name Bit Encoding Description
0x74 [7:0] r_tx_seed_a[23:16] Seed A value bit[23:16]
0x75 [7:0] r_tx_seed_a[31:24] Seed A value bit[31:24]
0x76 [7:0] r_tx_seed_a[39:32] Seed A value bit[39:32]
0x77 [7:0] r_tx_seed_a[47:40] Seed A value bit[47:40]
0x78 [7:0] r_tx_seed_a[55:48] Seed A value bit[55:48]
0x79 [1:0] r_tx_seed_a[57:56] Seed A value bit[57:56]
0x7A [7:0] r_tx_seed_b[7:0] Seed B value bit[7:0]
0x7B [7:0] r_tx_seed_b[15:8] Seed B value bit[15:8]
0x7C [7:0] r_tx_seed_b[23:16] Seed B value bit[23:16]
0x7D [7:0] r_tx_seed_b[31:24] Seed B value bit[31:24]
0x7E [7:0] r_tx_seed_b[39:32] Seed B value bit[39:32]
0x7F [7:0] r_tx_seed_b[47:40] Seed B value bit[47:40]
0x80 [7:0] r_tx_seed_b[55:48] Seed B value bit[55:48]
0x81 [1:0] r_tx_seed_b[57:56] Seed B value bit[57:56]
0x82
[0] r_tx_data_pat_sel
1'b0 2 local faults
1'b1 0's
[1] r_tx_test_pat_sel
1'b0 Pseudo Random
1'b1 Square Wave
[3] r_tx_test_en 1'b1
0x97 [2] r_rx_test_en 1'b1
0xAC [0] r_rx_test_pat_sel
1'b0 Pseudo random
1'b1 Square wave
0xD7 [7:0] random_err_cnt[7:0] Error count
0xD8 [7:0] random_err_cnt[7:0]
Timing Closure Recommendations
Altera recommends that you enable the multiple reconfiguration profiles feature in the Native PHY IP if
any of the modified or target configurations involve changes to PCS settings. Using multiple
reconfiguration profiles is optional if the reconfiguration involves changes to only PMA settings such as
PLL switching, CGB divider switching, and refclk switching. When you enable multiple reconfiguration
profiles, the Quartus II TimeQuest Timing Analyzer includes the necessary PCS timing arcs for all profiles
UG-01143
2015.05.11
Timing Closure Recommendations
6-55
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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