User guide

Table 6-35: Register Map for PRBS Pattern Inversion
Reconfiguration
Address (HEX)
Reconfigu‐
ration Bit
Attribute Name Bit Encoding Description
0x7 [2] tx_static_polarity_inversion
1'b0 Disables static polarity
inversion
1'b1 Enables static polarity
inversion
0xA [4] rx_static_polarity_inversion
1'b0 Disables static polarity
inversion
1'b1 Enables static polarity
inversion
Disable the inversion bit on the transmitter and receiver to prevent normal data traffic from being
inverted while entering or leaving the PCS.
Using Pseudo Random Pattern Mode
You can use the Arria 10 Pseudo Random Pattern (PRP) generator and verifier in the scrambler and
descrambler to generate random data pattern and seed that the scrambler can use. PRP mode is a test
mode of the scrambler. Two seeds are available to seed the scrambler: all 0s or two local fault-ordered sets.
The seed is used in the scrambler to produce the pattern. The r_tx_data_pat_sel is the data pattern that
the scrambler will scramble. PRP is only available when the scrambler is enabled. The PRP verifier shares
the rx_prbs_err error signal with PRBS. The error count can be read out from the corresponding
registers.
Enabling Pseudo Random Pattern Mode
You must perform a sequence of read-modify-writes to the reconfiguration interface to enable the Pseudo
Random Pattern. The read-modify-writes are required to addresses 0x082, 0x097, and 0x0AC. To enable
the Pseudo Random Pattern, complete the following steps:
1. Write 0x02 to address 0x000 of the channel.
2. Perform a read-modify-write to address 0x082 according to Table 6-36.
3. Perform a read-modify-write to address 0x097 according to Table 6-36.
4. Perform a read-modify-write to address 0x0AC according to Table 6-36.
5. Perform a reset.
6. Write 0x03 to address 0x000 of the channel.
To disable the PRP verifier write the original values back to the read-modify-write addresses listed
above.
Table 6-36: Register Map for Pseudo Random Pattern Mode
Reconfigura‐
tion Address
(HEX)
Reconfigura‐
tion Bit
Attribute Name Bit Encoding Description
0x72 [7:0] r_tx_seed_a[7:0] Seed A value bit[7:0]
0x73 [7:0] r_tx_seed_a[15:8] Seed A value bit[15:8]
6-54
Using Pseudo Random Pattern Mode
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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