User guide

PRBS Soft Accumulators
The Pseudo Random Binary Sequence (PRBS) soft accumulators are used in conjunction with the hard
PRBS blocks in the transceiver channel. This section describes the soft logic that can be added to the
Native PHY IP core. To enable this option, turn on the Enable PRBS Soft Accumulators option in the
Native PHY IP Parameter Editor.
The PRBS has three control bits (Enable, Reset, and Snapshot) and one status bit (PRBS Done).
• Enable bit—used to turn on the accumulation logic. This bit is also used for selective error accumula‐
tion and to pause the sequence.
• Reset bit—resets the PRBS polynomial and the bit and error accumulators. It also resets the snapshot
registers if independent channel snapshots are used.
• Snapshot bit—captures the current value of the accumulated bits and the errors simultaneously. This
neutralizes the impact of the added read time when the Avalon-MM interface is used. Capturing a
snapshot provides an accurate error count with respect to the bit count at a specific time.
• PRBS Done bit—indicates the PRBS checker has had sufficient time to lock to the incoming pattern.
For example, to capture the accumulated errors at any instance of time and read them back, you can
perform the following operations.
1. Perform read-modify-write to address 0x300 and set bit 0 to 1'b1. This action enables the error and bit
counters.
2. To capture the errors accumulated at a particular instant, perform read-modify-write to address 0x300
and set bit 2 to 1'b1. This takes a snapshot of the error counters and stores the value to the error count
registers.
3. To read the number of errors accumulated when the snapshot was captured, perform a read from the
corresponding error registers 0x301 to 0x307.
4. To reset the bit and error accumulators, perform a read-modify-write to address 0x300 bit 1.
Note:
You can enable the error and bit counters (0x300[0]) and capture the accumulated bits and errors
at different times. The error count registers and bit count registers are updated with the latest
counter values as long as the counter enable bit is set.
Table 6-29: PRBS Accumulator Registers
Address Type Name Description
0x300[0] RW Counter enable (enables both
error and bit counters)
Counter enable (enables both error and
bit counters)
0x300[1] RW Reset Reset the error accumulators
0x300[2] RW Error Count Snapshot Snapshot captures the current value of
accumulated bits and the errors at that
time instance
0x300[3] RO PRBS Done PRBS Done when asserted indicates the
verifier has captured consecutive PRBS
patterns and first pass of polynomial is
complete
0x301[7:0] RO Accumulated error count [7:0] Accumulated error count [7:0]
0x302[7:0] RO Accumulated error count [15:8] Accumulated error count [15:8]
0x303[7:0] RO Accumulated error count
[23:16]
Accumulated error count [23:16]
6-44
PRBS Soft Accumulators
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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