User guide

Address Type Register Description
0x2E2[6] RW override_tx_
analogreset
Selects whether the receiver listens to the
ADME tx_analogreset register or the tx_
analogreset port. 1'b1 indicates the receiver
listens to the ADME tx_analogreset
register.
0x2E2[7] RW override_tx_
digitalreset
Selects whether the receiver listens to the
ADME tx_digitalreset register or the tx_
digitalreset port. 1'b1 indicates the
receiver listens to the ADME tx_digital-
reset register.
Table 6-26: Status Registers for the Native PHY IP Core
Address Type Register Description
0x280[0] RO rx_is_lockedtodata Shows the status of the current channel’s rx_
is_lockedtodata signal. 1’b1 indicates the
receiver is locked to the incoming data.
0x280[1] RO rx_is_lockedtoref Shows the status of the current channel’s rx_
is_lockedtoref signal. 1’b1 indicates the
receiver is locked to the reference clock.
0x281[0] RO tx_cal_busy Shows the status of the transmitter calibra‐
tion status. 1’b1 indicates the transmitter
calibration is in progress.
0x281[1] RO rx_cal_busy Shows the status of the receiver calibration
status. 1’b1 indicates the receiver calibration
is in progress.
The following control and status registers are available for the PLL IP cores.
Table 6-27: Control Registers for the PLL IP Cores
Address Type Register Description
0x2E0[0] RW pll_powerdown Drives the PLL powerdown when the
Override is set.
0x2E0[1] RW override_pll_
powerdown
Selects whether the receiver listens to the
ADME pll_powerdown register or the pll_
powerdown port. 1’b1 indicates the receiver
will listen to the ADME pll_powerdown.
Table 6-28: Status Registers for the PLL IP Cores
Address Type Register Description
0x280[0] RO pll_locked Indicates if the PLL is locked. 1'b1 indicates
the PLL is locked.
0x280[1] RO pll_cal_busy Indicates the calibration status. 1'b1 indicates
the PLL is currently being calibrated.
UG-01143
2015.05.11
Control and Status Registers
6-43
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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