User guide

The following control and status registers are available for the Native PHY IP core.
Table 6-25: Control Registers for the Native PHY IP Core
Address Type Register Description
0x2E0[0] RW set_rx_locktodata Asserts the set_rx_locktodata signal to the
receiver. 1'b1 sets the ADME set_rx_
locktodata register. See override_set_rx_
locktodata.
0x2E0[1] RW set_rx_locktoref Asserts the set_rx_locktoref signal to the
receiver. 1'b1 sets the ADME set_rx_
locktoref register. See override_set_rx_
locktoref row below.
0x2E0[2] RW override_set_rx_
locktodata
Selects whether the receiver listens to the
ADME set_rx_locktodata register or the
rx_set_locktodata port. 1'b1 indicates that
the receiver listens to the ADME set_rx_
locktodata register.
0x2E0[3] RW override_set_rx_
locktoref
Selects whether the receiver is listens to the
AMDE set_rx_locktoref register or the
rx_set_locktoref port. 1'b1 indicates that
the receiver listens to the ADME set_rx_
locktoref register.
0x2E1[0] RW rx_seriallpbken Enables the rx_seriallopbken feature in the
transceiver. 1’b1 enables reverse serial
loopback.
0x2E2[0] RW rx_analogreset Drives rx_analogreset when the override is
set.
0x2E2[1] RW rx_digitalreset Drives rx_digitalreset when the override
is set.
0x2E2[2] RW tx_analogreset Drives tx_analogreset when the override is
set.
0x2E2[3] RW tx_digitalreset Drives tx_digitalreset when the override
is set.
0x2E2[4] RW override_rx_
analogreset
Selects whether the receiver listens to the
ADME rx_analogreset register or the rx_
analogreset port. 1'b1 indicates the receiver
listens to the ADME rx_analogreset
register.
0x2E2[5] RW override_rx_
digitalreset
Selects whether the receiver listens to the
ADME rx_digitalreset register or the rx_
digitalreset port. 1'b1 indicates the
receiver listens to the ADME rx_digital-
reset register.
6-42
Control and Status Registers
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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