User guide

Table 6-23: Capability Registers for the Native PHY IP Core
Address Type Name Description
0x200[7:0] RO IP Identifier Unique identifier for the Native PHY IP
instance.
0x204[0] RO Status Register Enabled Indicates whether the status registers have
been enabled. 1'b1 indicates that the status
registers are enabled.
0x205[0] RO Control Register
Enabled
Indicates whether the control registers have
been enabled. 1'b1 indicates that the control
registers are enabled.
0x210[7:0] RO Number of Channels Shows the number of channels specified for
the Native PHY IP instance.
0x211[7:0] RO Channel Number Shows the unique channel number.
0x212[7:0] RO Duplex Shows the transceiver mode:
• 2'b00 = Unused
• 2'b01 = TX
• 2'b10 = RX
• 2'b11 = Duplex
0x213[0] RO PRBS Soft Enabled Indicates whether the PRBS soft accumula‐
tors are enabled. 1’b1 indicates the accumula‐
tors are enabled.
0x214[0] RO ODI Acceleration Logic
Enabled
Indicates whether the ODI acceleration logic
is enabled. 1’b1 indicates the feature is
enabled.
The following capability registers are available for the PLL IP cores.
Table 6-24: Capability Registers for the PLL IP Cores
Address Type Name Description
0x200[7:0] RO IP Identifier Unique identifier for the PLL IP instance.
0x204[0] RO Status Register Enabled Indicates if the status registers have been
enabled or not. 1'b1 indicates that the status
registers have been enabled.
0x205[0] RO Control Register
Enabled
Indicates if the control registers have been
enabled or not. 1'b1 indicates that the control
registers have been enabled.
0x210[7:0] RO Master CGB Enabled Indicates if the Master Clock Generation
Block has been enabled. 1'b1 indicates the
master CGB is enabled.
Control and Status Registers
Control and status registers are optional registers that memory-map some of the status outputs from and
control inputs to the Native PHY and PLL.
UG-01143
2015.05.11
Control and Status Registers
6-41
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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