User guide

e. Set Status Selection in address 0x144 to 6’h2C to select the ODI Pattern Error bits[15:8] in Status
value.
f. Read Status value in address 0x177 to get the Pattern Error bits[15:8].
g. Set Status Selection in address 0x144 to 6’h2B to select the ODI Pattern Error bits[7:0] in Status
value.
h. Read Status value in address 0x177 to get Pattern Error bits[7:0].
i. You can repeat step “2.e.ii” to check whether more patterns are required.
Embedded Debug Features
The Arria 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores provide the following
optional debug features to facilitate embedded test and debug capability:
• Altera Debug Master Endpoint (ADME)
• Optional Reconfiguration Logic
Altera Debug Master Endpoint
The ADME is a JTAG-based Avalon Memory-Mapped (Avalon-MM) master that provides access to the
transceiver and PLL registers through the system console. You can enable ADME using the Enable Altera
Debug Master Endpoint option available under the Dynamic Reconfiguration tab in the Native PHY
and PLL IPs. When using ADME, the Quartus II software inserts the debug interconnect fabric to connect
with USB, JTAG, or other net hosts. Select the Share Reconfiguration Interface parameter when the
Native PHY IP instance has more than one channel.
Optional Reconfiguration Logic
The Arria 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores contain soft logic for
debug purposes known as the Optional Reconfiguration Logic. This soft logic provides a set of registers
that enable you to determine the state of the Native PHY and PLL IP cores.
You can enable the following optional reconfiguration logic options in the transceiver Native PHY and
PLL IP cores:
• Capability registers
• Control and status registers
• PRBS soft accumulators
• ODI acceleration logic
Capability Registers
The capability registers provide high level information about the transceiver channel and PLL
configuration.
The capability registers capture a set of chosen capabilities of the PHY that cannot be reconfigured. The
following capability registers are available for the Native PHY IP.
6-40
Embedded Debug Features
UG-01143
2015.05.11
Altera Corporation
Reconfiguration Interface and Dynamic Reconfiguration
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