User guide

Port Name Direction Clock Domain Description
reconfig_readdata[N*32-1:0] Output reconfig_clk A 32-bit data read bus for each channel.
Valid data is placed on this bus after a
read operation. Signal is valid after
waitrequest goes high and then low.
reconfig_waitrequest[N-1:0] Output reconfig_clk A one-bit signal for each channel that
indicates the Avalon interface is busy.
Keep the Avalon command asserted
until this signal goes low.
Table 6-18: Avalon Interface Parameters
The following parameters are available in the Dynamic Reconfiguration tab of the Transceiver Native PHY and
TX PLL parameter editors.
Parameter Value Description
Enable dynamic reconfigura‐
tion
On / Off Enables the reconfiguration interface. Off by default. The
reconfiguration interface is exposed when this option is
enabled.
Share reconfiguration
interface
On / Off Enables you to use a single reconfiguration interface to
control all channels. Off by default. If enabled, the
uppermost bits of reconfig_address identifies the
active channel. The lower 10 bits specify the reconfigura‐
tion address. Binary encoding is used to identify the
active channel (available only for Transceiver Native
PHY). Enable this option if the Native PHY is configured
with more than one channel.
Enable Altera Debug Master
Endpoint
On / Off When enabled, the Altera Debug Master Endpoint
(ADME) is instantiated and has access to the Avalon-
MM interface of the Native PHY. You can access certain
test and debug functions using System Console with the
ADME. Refer to the Embedded Debug Features section
for more details about ADME.
Enable capability registers On / Off Enables capability registers. These registers provide high-
level information about the transceiver channel's
configuration.
Set user-defined IP identifier User-
specified
Sets a user-defined numeric identifier that can be read
from the user_identifier offset when the capability
registers are enabled.
Enable control and status
registers
On / Off Enables soft registers for reading status signals and
writing control signals on the PHY interface through the
ADME or reconfiguration interface.
Enable PRBS soft accumula‐
tors
On / Off Enables soft logic to perform PRBS bit and error
accumulation when using the hard PRBS generator and
checker.
UG-01143
2015.05.11
Ports and Parameters
6-27
Reconfiguration Interface and Dynamic Reconfiguration
Altera Corporation
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