User guide

Transceiver Configuration
Setting
Description
Basic/Custom w /Rate
Match (Standard PCS)
Enforces a standard set of rules including rules for the Rate Match FIFO
within the Standard PCS. Select these rules to implement custom protocols
requiring blocks within the Standard PCS or protocols not covered by the
other configuration rules.
CPRI (Auto) Enforces rules required by the CPRI protocol. The receiver word aligner
mode is set to Auto. In Auto mode, the word aligner is set to deterministic
latency.
CPRI (Manual) Enforces rules required by the CPRI protocol. The receiver word aligner
mode is set to Manual. In Manual mode, logic in the FPGA fabric controls
the word aligner.
GbE Enforces rules that the 1 Gbps Ethernet (1 GbE) protocol requires.
GbE 1588 Enforces rules for the 1 GbE protocol with support for Precision time
protocol (PTP) as defined in the IEEE 1588 Standard.
Gen1 PIPE Enforces rules for a Gen1 PCIe
®
PIPE interface that you can connect to a
soft MAC and Data Link Layer.
Gen2 PIPE Enforces rules for a Gen2 PCIe PIPE interface that you can connect to a
soft MAC and Data Link Layer.
Gen3 PIPE Enforces rules for a Gen3 PCIe PIPE interface that you can connect to a
soft MAC and Data Link Layer.
Basic (Enhanced PCS) Enforces a standard set of rules within the Enhanced PCS. Select these rules
to implement protocols requiring blocks within the Enhanced PCS or
protocols not covered by the other configuration rules.
Interlaken Enforces rules required by the Interlaken protocol.
10GBASE-R Enforces rules required by the 10GBASE-R protocol.
10GBASE-R 1588 Enforces rules required by the 10GBASE-R protocol with 1588 enabled.
10GBASE-R w/KR FEC Enforces rules required by the 10GBASE-R protocol with KR FEC block
enabled.
40GBASE-R w/KR FEC Enforces rules required by the 40GBASE-R protocol with the KR FEC
block enabled.
Basic w/KR FEC Enforces a standard set of rules required by the Enhanced PCS when you
enable the KR FEC block. Select this rule to implement custom protocols
requiring blocks within the Enhanced PCS or protocols not covered by the
other configuration rules.
PCS Direct Enforces rules required by the PCS Direct mode. In this configuration the
data flows through the PCS channel, but all the internal PCS blocks are
bypassed. If required, the PCS functionality can be implemented in the
FPGA fabric.
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General and Datapath Parameters
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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